Call for Papers
The goal of this workshop is to provide a forum to discuss new and emerging general-purpose purpose programming environments and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s workshop is particularly interested in exploring new heterogeneous GPU platforms, new forms of concurrency, and novel/irregular applications that can leverage these platforms. Papers are being sought on many aspects of GPUs, including (but not limited to):
- GPU applications
- GPU programming environments
- GPU runtime systems
- GPU compilation
- GPU architectures
- Multi-GPU systems
- GPU power/efficiency
- GPU reliability
- GPU benchmarking/measurements
- Heterogeneous GPU platforms that incorporate GPUs
- Papers due: December 1, 2015 (paper submission closed)
- Notification: December 21, 2015
- Final paper due: January 4, 2015
All submissions must be made electronically through the EasyChair system. Full paper submissions must be in PDF formatted for US lettersize paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX here (use the 9 pt template). Authors can choose to reveal their identity (or not) in submitted papers. All accepted papers will be published in the ACM Online Conference Proceedings Series. For questions, contact David Kaeli firstname.lastname@example.org.
US National Science Foundation (NSF) Support The US National Science Foundation has provided funding to support student attendance at PPoPP 2016. Applicants must be registered students at accredited US academic institutions. Successful applicants will be reimbursed for approved expenses, including travel, accommodation, and reasonable meal expenses. All reimbursements will require original receipts. Instructions on filing for reimbursement will be provided to successful applicants.
Application can be made at http://goo.gl/forms/cK0gOAIOHP.
Support from NSF is provided through Grant CCF-1552229. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
The ACM SIGPLAN PAC Funds support travel and accommodation for Students who have a paper at the conference or associated workshops, see http://www.sigplan.org/PAC/ for additional details.
For students who are not eligible for the NSF support or PAC funding; PPoPP has set up a scholarship. If your institution is unable to fund you for attending the conference; please fill this form: http://goo.gl/forms/cK0gOAIOHP Priority will be given to :
- Students who submitted a paper to PPoPP
- Students who submitted a paper at a workshop
- Students who wish to attend the conference
We will require a letter of recommendation from your Advisor. Notifications will be sent early in March.
Sat 12 Mar
|09:00 - 09:45|
|09:45 - 10:05|
|10:05 - 10:25|
|11:00 - 11:20|
|11:20 - 11:40|
|11:40 - 12:00|
|14:00 - 14:45|
|14:45 - 15:05|
|15:05 - 15:25|
|16:00 - 16:40|
|16:40 - 17:00|
|17:00 - 17:20|
|17:20 - 17:30|
Links to accepted papers
GPGPU '16- Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing UnitFull Citation in the ACM Digital Library
SESSION: Heterogenous languages, extensions and runtimes
SESSION: Tasking and scheduling
SESSION: Stencil optimization
Mateo Valero, Universitat Politécnica de Catalunya
In the last years the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while computer architects proposed techniques to aggressively exploit Instruction-Level Parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors on a chip. While these designs are able to compensate the clock frequency stagnation, they face multiple problems in terms of power consumption, programmability, resilience or memory. The solution is to give more responsibility to the runtime system and to let it tightly collaborate with the hardware. The runtime has to drive the design of future multi-cores architectures. In this talk, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime’s perspective.
Mateo Valero, http://www.bsc.es/cv-mateo/, obtained his Telecommunication Engineering Degree from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Telecommunications from the Technical University of Catalonia (UPC) in 1980. He is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and he has given more than 400 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.
Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award 2007 by the IEEE and ACM; Seymour Cray Award 2015 by IEEE; Harry Goode Award 2009 by IEEE: ACM Distinguished Service Award 2012; Euro-Par Achievement Award 2015; the Spanish National Julio Rey Pastor award, in recognition of research in Mathematics; the Spanish National Award “Leonardo Torres Quevedo” that recognizes research in engineering; the “King Jaime I” in basic research given by Generalitat Valenciana; the Research Award by the Catalan Foundation for Research and Innovation and the “Aragón Award” 2008 given by the Government of Aragón. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria, Zaragoza, Complutense de Madrid, Cantabria and Granada in Spain and by the University of Veracruz in Mexico. “Hall of the Fame” member of the ICT European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon, November 2008)
In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondant Academic of the Spanish Royal Academy of Science, in 2006 member of the Royal Spanish Academy of Doctors, in 2008 member of the Academia Europaea and in 2012 Correspondant Academic of the Mexican Academy of Sciences. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow.
In 1998 he won a “Favourite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.
Andrew Richards, Codeplay Software Ltd,
We can now say that almost all future performance improvements will come from heterogeneous acceleration. But the reality of building successful software and platforms is that no one company or individual can create everything. That means we need to provide standard platforms, interfaces, tools, languages and components that interoperate. Only through open standards can we all innovate in our own specialist areas. What are the challenges, opportunities and requirements of working together to allow software components, languages, tools and processor cores from different researchers and companies to play nice together?
As well as being CEO and Founder of Codeplay Software Ltd, Andrew is also the Chair of the Tools and System Runtime working groups of the HSA Foundation and the Chair of the SYCL™ for OpenCL™ Group of the Khronos Group. After graduating from Cambridge University with a degree in Computer Science and Physics, Andrew started his career in the 8-bit days writing videogames, before researching compiler technology and founding Codeplay in 2002. Codeplay have been producing compilers for games consoles, special-purpose processors and GPUs since then. Today Codeplay is a world-leading specialist in GPU compiler technology, working on high-end mobile graphics and research into future graphics and processing technologies.