A new SIMD iterative connected component labeling algorithm
This talk presents a new multi-pass iterative algorithm for Connected Component Labeling. The performance of this algorithm is compared to those of State-of-the-Art two-pass direct algorithms. We show that thanks to the parallelism of the SIMD multi-core processors and an activity matrix that avoids useless memory access, such a kind of algorithm has performance that comes closer and closer to direct ones. This new tiled iterative algorithm has been benchmarked on four generations of Intel Xeon processors: 2×4- core Nehalem, 2×12-core Ivy-Bridge, 2×14-core Haswell and 57-core Knight Corner. Macro meta-programming was used to design a unique code for SSE, AVX2 and KNC SIMD instruction set.
Sun 13 Mar (GMT+01:00) Greenwich Mean Time : Belfast change
|09:00 - 09:15|
Jan EitzingerUniversity of Erlangen-Nuremberg, Germany
|09:15 - 10:00|
|10:00 - 10:30|
Lionel LacassagneUniversity Paris 6